clocked signal造句

• The transition from voltage to no voltage is referred to as the trailing edge of a clock signal .
  电感从一定值下降到0值的跃迁叫做时钟信号的后沿。
• A clock signal with 1 million pulses per second is referred to as a 1 megahertz .
  每秒钟有一百万个脉冲及时钟信号，也称兆赫（）时钟信号。
• The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal .
  你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
• The device always generates the clock signal
  时钟信号总是由设备端生成的。
• Real - time power angle measurement of a synchronous generator based on gps clock signal and tachometer
  时钟信号的发电机功角实时测量方法
• A clock signal with 1 million pulses per second is referred to as a 1 megahertz
  每秒钟有一百万个脉冲及时钟信号，也称兆赫（ ? ）时钟信号。
• Oscillator generated a wave with frequency 132 khz as the clock signal
  振荡器电路产生一个频率在132khz附近抖动的矩形波作为整个电路的时钟信号。
• All signals , except for the clock signal , are limited in one block or between two adjacent blocks
  除了全局时钟之外的信号都被限定在一个模块内部或者相邻的2个模块之间。
• The tft lcm driver signals were enable signal and fiducial clock signal , which were strict with synchronization
  驱动信号主要为使能信号和基准时钟信号,并要求二者具有严格的同步性。
• Again , the keyboard / mouse always generates the clock signal , but the host always has ultimate control over communication
  重复一遍，键盘/鼠标总是生成时钟信号，而主机控制着整个通信过程。
• By means of modulating the clock signal input of hef4752 , six spwm signals are produced
  Spwm信号产生电路以大规模集成电路? ? hef4752为核心，通过对输入的三路时钟信号的调制，得到六路spwm信号的输出。
• Data sent from the device to the host is read on the falling edge of the clock signal ; data sent from the host to the device is read on the rising edge
  从设备发送给主机的数据时在时钟信号的下降沿读取的;从主机发给设备的数据是在上升沿读取的。
• The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal , yet isolates the clock from the “ clock - used - as - data ” logic
  主要的方式是导入时钟隔离电路追踪时钟转换如时钟讯号，然后"时钟做为资料"逻辑做为隔离时钟技术。
• A kind of multi level model of clock binary tree and its construction algorithm of clock signal based on multi - level genetic algorithm were proposed
  摘要阐述了芯片的版图设计中形成时钟二叉树的多级遗传算法，从理论上说明了该遗传算法的求解思路、编码方式、适应度函数、遗传算子的设计等。
• The third , the whole circuit of digital cmos image sensor is presented . the circuits of pixel array , clock signal generator and sam have been improved on the base of simulation
  再次，我们对整个cmos数字图像传感器进行了电路设计，主要包括：时钟信号发生器，顺序移位寄存器和像素阵列。
• The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5
  电平调节电路100将送往第一个时钟终端ck1的时钟信号从h电平降低一个预定值，并将此信号送往晶体管q5的输入端。
• And should design proper circuit structure or then - mixed structure to meet the technical required . to produce high speed , robust clock signal is the aim of this research
  电路设计中针对深亚微米coms电路的特点，综合考虑速度、功耗、面积等因素，选用适当的电路形式或其组合结构，以满足设计要求。
• The main research contents of this dissertation are shown in the following : ( 1 ) introduce one method of use the counting pulse to develop ie measuring system and new method of using the high frequency clock signal to divide the space pulse
  本文主要研究内容如下: ( 1 )系统论述了一个脉冲计数方式的ie测量系统的测量原理,阐述了一个采用高频的时钟信号细分空间脉冲的新型细分方法。
• At the base of earnestly analysis to the ov7620 working sequence , using its frame synchronization , field synchronization and the pixel - clock signal , completed gathering of the active power meter reading image which is reduced resolutions at the control of mcu
  在仔细分析ov7620工作时序的基础上,利用其帧同步、场同步和像素时钟信号,在单片机的控制下完成了对电度表读数图像的降低分辨率采集。
• The following is main content of our thesis . the first , we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ) . it is made up of three sections : pixel array , clock signal generator and sam ( sequential access memory )
  本文的主要内容如下：首先，我们对像素级a d转换型图像传感器的系统工作原理进行了分析，是由像素阵列、时钟信号产生器和sam (顺序读写存储器)三部分构成的。